1. Field of the Invention
The present invention relates to the field of displaying technology, and in particular to a method for manufacturing a thin-film transistor (TFT) substrate and a structure thereof.
2. The Related Arts
In the field of displaying technology, flat panel display technology, such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), has gradually taken the place of cathode ray tube (CRT) displays, and among them, the OLEDs have various advantages, such as being self-luminous, low driving voltage, high light emission efficiency, short response time, high clarity and contrast, virtually 180° view angle, wide temperature range of applications, being capable of flexible displaying, and full color displaying in a large area, and are considered a display device with the best potential of development.
The OLEDs can be classified, according to the type of driving, as passive OLEDs (such as passive matrix OLEDs (PMOLEDs)) and active OLEDs (such as active matrix OLEDs (AMOLEDs)). An AMOLED device is driven by electrical current and thus has a severe requirement for the electrical current of thin-film transistors. Thus, an AMOLED product must comprise a pixel compensation circuit to reduce current variation resulting from instability of TFT in the entire driving process.
A conventional AMOLED pixel compensation circuit often involves multiple TFT connected in series. For example, FIG. 1 illustrates a pixel compensation circuit, which comprises two TFTs, namely TFT1 and TFT2, connected in series between two signal lines that are a data line Vdata and a voltage supply line Vdd. FIG. 2 illustrates a TFT substrate structure corresponding to the pixel compensation circuit shown in FIG. 1. FIG. 3 is a schematic view illustrating the arrangement and connection of the TFT components of the TFT substrate structure shown in FIG. 2 with the data line and the voltage supply line.
As shown in FIGS. 2 and 3, the TFT substrate structure comprises, in sequence from bottom to top, a substrate 100, a first metal layer, a gate insulation layer 300, a semiconductor layer, an etch stop layer 500, and a second metal layer. The first metal layer comprises a first gate terminal 210 and a second gate terminal 230 that are spaced from each other. The semiconductor layer comprises a first semiconductor 420 and a second semiconductor 440 that are spaced from each other. The second metal layer comprises a first source terminal 610, a connection electrode 620, and a second drain terminal 630.
The etch stop layer 500 comprises a first through hole 510, a second through hole 520, a third through hole 530, and a fourth through hole 540 formed therein. The first source terminal 610 is set in contact with an end of the first semiconductor 420 via the first through hole 510. The connection electrode 620 is set in contact with an opposite end of the first semiconductor 420 via the second through hole 520 and is also set in contact with an end of the second semiconductor 440 via the third through hole 530. The second drain terminal 630 is set in contact with an opposite end of the second semiconductor 440 via the fourth through hole 540.
The first gate terminal 210, the first semiconductor 420, the first source terminal 610, and the connection electrode 620 collectively form a first TFT; and the second gate terminal 230, the second semiconductor 440, the connection electrode 620, and the second drain terminal 630 collectively form a second TFT.
As shown in FIGS. 2 and 3, the connection electrode 620 simultaneously serves as a first drain terminal for the first TFT and a second source terminal for the second TFT so as to seriously connect the first TFT and the second TFT. However, the second metal layer on which the connection electrode 620 is located also comprises signal lines, such as the data line Vdata and the voltage supply line Vdd, the design rule for the connection electrode 620 is very narrow and in addition, the bridging between the two TFT through the connection electrode 620 would further narrow the design rule of the second metal layer and thus making it adverse to the manufacture of a display panel with a high aperture ratio and high definition.